伊藤 信之   Nobuyuki ITOH

講座・コース 情報電子工学講座 Nobuyuki ITOH
役職 教授
生年月 1960年03月生
自室番号 2407
Email nobby**c.oka-pu.ac.jp
※利用の際は,** を @に置き換えてください.
学歴 東京理科大学理学部化学科(1983年3月)
東京理科大学理学研究科化学専攻(修)(1985年3月)
学位 博士(工学)東京工業大学,2006年7月,
無線通信用CMOS電圧制御LC発振器の低位相雑音化に関する研究
資格・免許 第一種衛生管理者
着任年月 2010年10月
職歴 (株)東芝(1985年4月~2010年9月)
中央大学理工学部非常勤講師(2009年4月~2011年3月)
専門分野 集積回路工学
所属学協会 電子情報通信学会,IEEE
現在の研究テーマ 高周波アナログCMOS集積回路設計,高周波デバイスモデリング
主要担当科目
 学部 集積回路, 電気回路Ⅰ, 半導体工学Ⅱ
 大学院 アナログ集積回路設計特論, 電子情報回路特論, アナログ集積回路設計特論
相談・共同研究可能
なテーマ
RFCMOSを中心とする高周波アナログ回路と高周波モデリング、アナログ集積回路一般
研究概要 【1】無線通信LSIのための電圧制御発振器の低位相雑音化に関する研究
N.Itoh, et. al., "A Study of Striped Inductor for K- and Ka-band Voltage-controlled Oscillators,” IEICE Transaction on Electronics, Vol.E99-C, No.6, Jun. 2016 掲載決定. 他学術論文7件
【2】無線通信LSIのためのデバイスモデルの研究
Y.Itano, N.Itoh, et. al.,"High-Q MOS Varactor Models for Quasi-Millimeter-Wave Low-Noise LC-VCOs,"IEICE Transaction on Fundamentals, vol. E97-A, No.3, pp. 759-767, Mar. 2014.  他学術論文4件
【3】無線通信トランシーバLSIに関する研究
T. Ogawa, N.Itoh, et. al., "A Study of Current-Reuse Concurrent Receiver Amplifier," IEICE Transaction on Fundamentals, Vol.J99-A, No.8, Aug. 2016 掲載決定. 他学術論文10件
【4】高速論理回路のためのデバイス・回路の研究
T.Iinuma, N.Itoh, et. al., "Sub-20 ps High-Speed ECL Bipolar Transistor with Low Parasitic Architecture," IEEE Trans. Elec. Devices., vol. ED-42, No. 3, pp.399-405, Mar. 1995. 他学術論文2件
社会における活動 1. IEEE CICC (Custom Integrated Circuits Conference) TPC
2. IEEE BCTM (Bipolar/BiCMOS Circuits and Technology Meeting) TPC
3. IEEE ESSCIRC (European Solid-State Circuits Conference) TPC
4. KJMW (Korea-Japan Microwave Conference) Secretary
5. IEEE MTT-S Japan Chapter Secretary
6. USRI-C (UNion Radio Scientifique Intemationale Commission C) Japan Committee Secretary
7. APMC (Asia-Pacific Microwave Conference) Publicity Chair
8. 電子情報通信学会 Transaction 編集委員
9. IEEE RFIC (Radio Frequency Integrated Circuits Symposium) TPC
10. 電子情報通信学会 集積回路研究会 専門委員
11. 電気学会 高周波集積回路の先端化技術と応用技術調査専門委員
12. IEEE RFIT(Radio Frequency Integration Technology) TPC
13. VJMW(Vietnam-Japan Microwave)TPC
受賞 APMC (Asia-Pacific Microwave Conference) 2007 Prize
研究業績 学術論文

J28. T. Ogawa, T. Morishita, K. Komoku, Y. Itano, S. Yoshitomi, and N. Itoh, “A Study of Current-Reuse Concurrent Receiver Amplifier,” To be published IEICE Transaction on Fundamentals, Vol.J99-A, No.8, pp.-, Aug. 2016.

J27. N. Itoh, H. Tsuji, Y. Itano, T. Morishita, K. Komoku, and S. Yoshitomi, “A Study of Striped Inductor for K- and Ka-band Voltage-controlled Oscillators,” To be published IEICE Transaction on Electronics, Vol.E99-C, No.6, pp.-, Jun. 2016.

J26. Y. Itano, S. Moromoto, S. Yoshitomi, and N. Itoh, "High-Q MOS Varactor Models for Quasi-Millimeter-Wave Low-Noise LC-VCOs," IEICE Transaction on Fundamentals, vol. E97-A, No.3, pp. 759-767, Mar. 2014.

J25. Q. Liu, J. Sun, Y-J. Suh, N. Itoh, and T. Yoshimasu, "A CMOS Class-G Supply Modulation for Polar Power Amplifiers with High Average Efficiency and Low Ripple Noise," IEICE Transaction on Fundamentals, vol. E95-A, No.1, pp. 487-497, Feb. 2012.

J24. Y. Feng, G. Takemura, S. Kawaguchi, N. Itoh, and P. R. Kinget, "Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers," IEEE Journal of Solid-State Circuits, Vol. 46, pp. 2253-2267, No. 10, Oct. 2011.

J23. Y. Takamatsu, R. Fujimoto, T. Sekine, T. Yasuda, M. Nakamura, T. Hirakawa, M. Ishii, M. Hayashi, H. Ito, Y. Wada, T. Imayama, T. Oomoto, Y. Ogasawara, M. Nichikawa, Y. Yoshida, K. Yoshioka, S. Saigusa, H. Yoshida, and N. Itoh, "A Single-Chip RF Tuner / OFDM Demodulator for Mobile Digital TV Application," IEICE Transaction on Electronics, vol. E94-C, No.4, pp. 557-566, Apr. 2011.

J22. Q. Liu, Y. Takigawa, S. Kurachi, N. Itoh and T. Yoshimasu, "A 1.2-3.2 GHz CMOS VCO IC Utilizing Transformer-Based Variable Inductors and AMOS Varactors, " IEICE Transaction on Fundamentals, vol. E94-A, No.2, pp. 568-573, Feb. 2011.

J21. J. Deguchi, D. Miyashita, Y. Ogasawara, G. Takemura, M. Iwanaga, K. Sami, R. Ito, J. Wadatsumi, Y. Tsuda, S. Oda, S. Kawaguchi, N. Itoh, M. Hamada, "A Fully Integrated 2X1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifer in 65 nm CMOS," IEEE Journal of Solid-State Circuits, Vol. 45, pp. 2774-2784, No. 12, Dec. 2010.

J20. K. Agawa, S. Ishizuka, H. Majima, H. Kobayashi, M. Koizumi, T. Nagano, M. Arai, Y. Shimizu, A. Maki, G. Urakawa, T. Terada, N. Itoh, M. Hamada, F. Fujii, T. Kato, S. Yoshitomi, and N. Otsuka, "A 0.13 um CMOS Bluetooth EDR Transceiver with High Sensitivity over Wide Temperature Range and Immunity to Process Variation," IEICE Transaction on Electronics, vol. E93-C, No.6, pp. 803-811, Jun. 2010.

J19. H. Yoshida, T. Toyoda, H. Tsurumi, and N. Itoh, "A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface," IEICE Transaction on Fundamentals, Vol. E93-A, No.2, pp. 375-381, Feb. 2010.

J18. 太田宙志,吉増敏彦,倉智聡,伊藤信之,米村浩二,”MOSFETとpn接合ダイオードにより構成される新しいバラクタ回路を用いた広帯域電圧制御発振器,” 電子情報通信学会論文誌 C, Vol. J91-C, No.12, pp.702-710, Dec. 2008.

J17. M. Bucher, A. Bazigos, S Yoshitomi, and N Itoh, "A Scalable Advanced RF IC Design-Oriented MOSFET Model," Int. Journal of RF and Microwave Computer Aided Engineering, Vol. 18, pp. 314-325, Jul. 2008 (DOI 10.1002).

J16. M. Nagata, H. Masuoka, S. Fukase, M. Kikuta, M. Morita, and N. Itoh, "A 5.8-GHz ETC Transceiver using SiGe-BiCMOS," IEICE Transaction on Electronics, vol. E90-C, No.9, pp.1721-1728, Sep. 2007.

J15. S. Kurachi, T. Yoshimasu, H. Liu, N. Itoh, and K. Yonemura, "A SiGe BiCMOS VCO IC with highly linear Kvco for 5-GHz Band Wireless LANs," IEICE Transaction of Electronics, vol. E90-C, No.6, pp.1228-1233, Jun. 2007.

J14. H. Liu, T. Yoshimasu, S. Kurachi, N. Itoh, and K. Yonemura, "A Novel Diode Linearizer for SiGe HBT Power Amplifier," John Wiley & Sons, Microwave and Optical Technology Letters, vol.48, No.8, pp.1535-1537, Aug. 2006.

J13. N. Itoh, K. Kojima, and T. Ohguro, "Channel Noise Enhancement in Small Geometry MOSEFT and Its Influence on Phase Noise Calculation of Integrated Voltage-Controlled-Oscillator," John Wiley & Sons, International Journal of Numerical Modelling, vol.18, No.4, pp.255-266, Jul. 2005.

J12. N. Itoh, K. Hirashiki, T. Terada, M. Kikuta, S. Ishizuka, T. Koto, T. Suzuki, and H. Aoki, "High Sensitivity 900-MHz ISM Band Transceiver," IEICE Transaction on Fundamentals, vol. E88-A, No.2, pp.498-506, Feb. 2005.

J11. N. Itoh, M. Nagata, and S. Yoshitomi. "Influence of Flip-Chip Assembly on On-chip Spiral Inductor," Int. Journal of RF and Microwave Computer Aided Engineering, vol.14, No.3, pp.236-243, May 2004.

J10. N. Itoh, "Low Voltage Low Phase Noise CMOS VCO and Its Flicker Noise Influence,"IEICE Transaction on Electronics, vol. E86-C, No.6, pp.1062-1068, Jun. 2003.

J9. N. Itoh, T. Ohguro, K. Katoh, H. Kimijima, S. Ishizuka, K. Kojima, and H. Miyakawa, "Scalable Parasitic Components Model of CMOS for RF Circuit Design," IEICE Transaction on Fundamentals, vol. E86-A, No.2, pp.288-298, Feb. 2003.

J8. N. Itoh, S. Ishizuka, K. Katoh, Y. Shimizu, and K. Yonemura, "A 38-% Tuning Range 6-GHz Fully Integrated VCO," IEICE Transaction on Electronics, vol. E85-C, No.8, pp.1604-1606, Aug. 2002.

J7. N. Itoh and S. Ishizuka, "1200-MHz Fully Integrated VCO with “Turbo-Charger” Technique," IEICE Transaction on Electronics, vol. E85-C, No.8, pp.1569-1576, Aug. 2002.

J6. M. Steyaert, J. Janssens, B. De Muer, M. Borremans, and N. Itoh, "A 2 Volt CMOS Cellular Transceiver Front-End," IEEE Journal of Solid-State Circuits, vol. 35, No. 12, pp.1895-1907, Dec. 2000.

J5. M. Steyaert, M. Borremans, J. Janssens, B. De Muer, N. Itoh, J. Craninckx, J. Crols, E. Morifuji, H. S. Momose, and W. Sansen, "A Single-Chip CMOS Transceiver Front-End for DCS-1800 Wireless Communications," Analog Integrated Circuits and Signal Processing, vol. 24, No. 2, pp.83-99, Aug. 2000.

J4. M. Saito, M. Ono, R. Fujimoto, H. Tanimoto, N. Ito, T. Yoshitomi, T. Ohguro, H. S. Momose, and H. Iwai, "0.15 um RF CMOS Technology Compatible with Logic CMOS for Low-Voltage Operation," IEEE Electron Device, vol. ED-45, No. 3, pp.737-742, Mar. 1998.

J3. T. Iinuma, N. Itoh, H. Nakajima, K. Inou, S. Matsuda, C. Yoshino, Y. Tsuboi, Y. Katsumata, and H. Iwai, "Sub-20 ps High-Speed ECL Bipolar Transistor with Low Parasitic Architecture," IEEE Trans. Electron Devices., vol. ED-42, No. 3, pp.399-405, Mar. 1995.

J2. S. Matsuda, N. Itoh, C. Yoshino, Y. Tsuboi, Y. Katsumata, and H. Iwai, "Mechanical Stress Analysis of Trench Isolation Using a Two-Dimensional Simulation," IEICE Trans. Electron., vol. E77-C, no.2, pp.124-128, Feb. 1994.

J1. Y. Ushiku, T. Kobayashi, A. Yoshida, N. Itoh, A. Nishiyama, and R. Nakata, "An Optimized 1.0 um CMOS Technology for Next Generation Channelless Gate Arrays," IEEE Journal of Solid-State Circuits, vol. 23, No. 2, pp.507-513, Apr. 1988.

国際会議論文

C56. T. Ogawa, T. Morishita, K. Komoku, Y. Itano, S. Yoshitomi, and N. Itoh, “A Study of Current-Reuse 800 MHz/1.9 GHz Concurrent Dual-Band Amplifier,” IEEE Radio and Wireless Symposium 2016 (RWS2016), pp.245-247, Austin, Jan. 2016.

C56. H. Tsuji, Y. Itano, K. Komoku, T. Morishita, S. Yoshitomi, and N. Itoh, "A Study of Flicker Noise Suppression of K-Band VCO using Striped Inductor," Proc. of the 2015 Asia-Pacific Microwave Conference (APMC2015), WE4E-1, Nanjing, Dec. 2015.

C55. Y. Sato, Y. Kondo, K. Komoku, T. Morishita, and N. Itoh, "A 24-GHz Low-Noise Amplifier in 180nm CMOS," Thailand-Japan MicroWave 2015, TH-10, Aug. 2015.

C54. T. A. Kurniawan, X. Yang, X. Xu, N. Itoh, T. Yoshimasu, "A 2.5-GHz Band, 0.75-V High Efficiency CMOS Power Amplifier IC With Third Harmonic Termination Technique in 0.18-um CMOS," IEEE Wireless and Microwave Technology Conference (WAMICON2015), pp.1-3, Florida, Apr. 2015.

C53. H. Tsuji, Y. Itano, K. Komoku, T. Morishita, S. Yoshitomi, and N. Itoh, "Millimeter-Wave VCO using Striped Inductor," Proc. of Asia-Pacific Microwave Conference (APMC2014) 2014, pp. 959-961, Sendai, Nov. 2014.

C52. N. Itoh, R. Ohnishi, Y. Itano, T. Ogawa, H. Tsuji, K. Komoku, T. Morishita, S. Yoshitomi, "Scalable Analytical MOSFET Model for Analog Cirtcuit Design," The 17th International Conference on Analog VLSI Circuits (AVIC2014), pp.272-275, Ho Chi Minh, Oct. 2014.

C51. N. Itoh, Y. Itano, S.Morimoto, S. Yoshitomi, "Striped Inductor for Quasi Millimeter Wave Voltage-Controlled Oscillator," Proc. of the 2013 Asia-Pacific Microwave Conference (APMC2013), pp.319-321, Seoul, Nov. 2013.

C50. Y. Itano, N. Itoh, S. Yoshitomi, H. Hoshino, "High-Q MOS-Varactor Modeling for mm-Wave VCOs," Proc. of the 2012 Asia-Pacific Microwave Conference (APMC2012), pp.202-204, Kaohsiung, Dec. 2012.

C49. Q. Liu, J. Sun, Y. Suh, K. Horie, N. Itoh, T. Yoshimasu, "A High Efficiency and High Linearity Power Amplifier Utilizing Post-Linearization Technique for 5.8 GHz DSRC Applications," IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications, pp.45-48, Jan. 2011.

C48. Q. Liu, Y. Zhao, J. Sun, S. Kurachi, N. Itoh, T. Yoshimasu, "An Ultra Low Power Consumption and Low Phase Noise VCO Operating in Sub-threshold Region," International Symposium on Signals, Systems and Electronics (ISSSE), Sep. 2010.

C47. T. Yamaji, J. Matsuno, H. Aoyama, M. Furuta, T. Takida, I. Akita, A. Kuroda, T. Itakura, N. Itoh, "A 6-phase Harmonic Rejection Down-Converter with Digital Assist," Digest of Technical papers of the Symposium on VLSI Circuits, Kyoto, pp. 181-182, Jun. 2010.

C46. J. Deguchi, D. Miyashita, Y. Ogasawara, G. Takemura, M. Iwanaga, K. Sami, R. Ito, J. Wadatsumi, Y. Tsuda, S. Oda, S. Kawaguchi, N. Itoh, M. Hamada, "A Fully Integrated 2×1 Dual-Band Direct-Conversion Transceiver with Dual-Mode Fractional Divider and Noise-Shaping TIA for Mobile WiMAX SoC in 65nm CMOS," Proc. of the 2010 IEEE International Solid-State Circuits Conference (ISSCC10), San Francisco, pp. 456-457, Feb. 2010.

C45. Y. Feng, G. Takemura, S. Kawaguchi, N. Itoh, and P. Kinget, "A Low-Power Low-Noise Direct-Conversion Front-End with Digitally Assisted IIP2 Background SelfCalibration," Proc. of the 2010 IEEE International Solid-State Circuits Conference (ISSCC10), San Francisco, pp. 70-71, Feb. 2010.

C44. Y. Suh, J. Sun, K. Horie, N. Itoh, and T. Yoshimasu, "Fully-Integrated Novel High Efficiency Linear CMOS Power Amplifier for 5.8 GHz ETC Applications," Proc. of the 2009 Asia-Pacific Microwave Conference (APMC2009), Singapore, Dec. 2009.

C43. Y. Takamatsu, R. Fujimoto, T.Yasuda, T. Sekine, T. Hirakawa, M. Ishii, M. Hayashi, and N. Itoh, "A Tunable Low-noise Amplifier for Digital TV Applications," Proc. of Technical papers of 2009 Asian Solid-State Circuits Conference (A-SSCC2009), Taipei, pp. 273-276, Nov. 2009.

C42. Q. Liu, J. Sun, S. Kurachi, N. Itoh, T. Yoshimasu, "A Switched-Inductors Based VCO with A Ultra-Wideband Tuning Range of 88 %," Proc. of 2009 IEEE 8th International Conference on ASIC (ASICON2009), Changsha, Mainland China, pp. 355-358, Oct. 2009.

C41. T. Sekine, R. Fujimoto, Y. Takamatsu, M. Nakamura, T. Hirakawa, M. Ishii, T. Yasuda, M. Hayashi, H. Itoh, Y. Wada, T. Imayama, T. Oomoto, Y. Ogasawara, S. Saigusa, M. Yano, M. Nishikawa, H. Yoshida, Y.Yoshida, K. Yoshioka, and N. Itoh, "A Single-Chip RF Tuner / OFDM Demodulator for Mobile Digital TV Application," Proc. of the 35th 2009 European Solid-State Circuits Conference (ESSCIRC2009), Athens, Greece, pp.188-191, Sep. 2009.

C40. Q. Liu, J. Sun, S. Kurachi, N. Itoh, T. Yoshimasu, "15 GHz-Band Low Phase-Noise LC-VCO with Second Harmonic Tunable Filtering Technique," Proc. of PIMRC (Personal, Inoor and Mobile Radio Communication Symposium) 2009, Tokyo, Sep. 2009.

C39. Q. Liu, J. Sun, Y. Suh, S. Kurachi, N. Itoh, T. Yoshimasu, "A Novel Current Reuse Wideband Amplifier Using 130 nm Si CMOS Technology for 22-29 GHz Applications," IEEE International Conference on Communications, Circuits and Systems Proceedings, pp.807-809, Jul. 2009.

C38. Y. Takigawa, H. Ohta, Q. Liu, S. Kurachi, N. Itoh, and T. Yoshimasu, "A 92.6 % Tuning Range VCO utilizing Simultaneously Controlling of Transformers and MOS Varactors using 0.13 um CMOS Technology," Proc. of 2009 RFIC symposium, Boston, pp.83-86, U.S.A., Jun. 2009.

C37. N. Itoh and M. Hamada, "RF-Analog Circuit Design in Scaled SoC," Proc. of 14th Asia and Pacific Design Automation Conference (ASP-DAC2009), Yokohama, pp.702-707, Jan. 2009.

C36. H. Yoshida, T. Toyoda, T. Yasuda, Y. Ogasawara, M. Ishii, T. Murasaki, G. Takemura, M. Iwanaga, T. Takida, Y. Araki, T. Hashimoto, K. Sami, T. Imayama, H. Shimizu, H. Kokatsu, Y. Tsuda, I. Tamura, H. Masuoka, M. Hosoya, R. Ito, H. Okuni, T. Kato, K. Sato, K. Nonin, K. Osawa, R. Fujimoto, S. Kawaguchi, H. Tsurumi, and N. Itoh, "A Single-Chip 8-Band CMOS Transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with Digital Interface," Proc. of the 34th 2008 European Solid-State Circuits Conference (ESSCIRC2008), Edinburgh, Scotland, pp.142-145, Sep. 2008.

C35. H. Ohta, Y. Ishikawa, S. Yong-ju, R. Fujimoto, N. Itoh, T. Yoshimasu, "High Dynamic Range Variable Gain Amplifier Using 130nm CMOS Technology for Tripleband W-CDMA Applications," Proc. of the 2008 International Conference on Microwave and Millimeter Wave (ICMMT2008), Nanjing, pp.139-142, Apr. 2008

C34. M. Hamada and N. Itoh, "Robust Design of Deep Sub-micron CMOS Wireless SoC," Proc. of 2008 IEEE Radio and Wireless Symposium (RWS2008), Orlando, FL, pp.61-64, Jan. 2008.

C33. N. Itoh, H. Masuoka, S. Fukase, K. Hirashiki, and M. Nagata, "Twisted Inductor VCO for Supressing On-chip Interferences," Proc. of the 2007 Asia-Pacific Microwave Conference (APMC2007), Bangkok, pp.365-368, Dec. 2007.

C32. N. Itoh, "15 of Years Innovation of Integrated Voltage-Controlled Oscillators on Silicon Process," Proc. of Asia-Pacific Microwave Conference (APMC2007), Bangkok, pp.349-352, Dec. 2007.

C31. S. Kurachi, Y. Murata, S. Ishikawa, N. Itoh, K. Yonermura, and T. Yoshimasu, "A 4-GHz Band Ultra-Wideband Voltage Controlled Oscillator IC using 0.35 μm SiGe BiCMOS Technology," Proc. of the 2007 IEEE Bipolar Circuit and Technology Meeting (BCTM2007), Boston, The United States, pp.9-12, Oct. 2007.

C30. K. Agawa, H. Majima, H. Kobayashi, M. Koizumi, S. Ishizuka, T. Nagano, M. Arai, Y. Shimizu, G. Urakawa, N. Itoh, M. Hamada, and N. Otsuka, "A -90dBm Sensitivity 0.13μm CMOS Bluetooth Transceiver Operating in Wide Temperature Range," Proc. of the 2007 IEEE Custom Integrated Circuits Conference (CICC2007), San Jose, pp.655-658, Sep. 2007.

C29. S. Kurachi, T. Yoshimasu, N. Itoh, and K. Yonemura, "5 GHz-Band Highly Linear VCO IC with a Novel Resonant Circuit," Proc. of the 2007 IEEE SiRF Symposium (SiRF2007), Long Beach, pp.285-288, Jan. 2007.

C28. N. Itoh, "Realization of Wireless SoC and beyond it ~ Reconfigurable Wireless SoC ~," Proc. of 2007 IEEE RWS (Radio and Wireless Symposium), Long Beach, Jan. 2007.

C27. M. Nagata, H. Masuoka, S. Fukase, M. Kikuta, M. Morita, and N. Itoh, "5.8 GHz RF transceiver LSI including on-chip matching circuits," Proc. of the 2006 IEEE Bipolar Circuit and Technology Meeting (BCTM2006), Maastricht, pp.263-266, Oct. 2006.

C26. J. Chen, T. Yoshimasu, H. Liu, N. Itoh, and K. Yonemura, "An Ultra-Wideband and Low-Power Amplifier Using 0.35-um SiGe BiCMOS Technology," Proc. of the 2006 International Conference on Communications Circuits and Systems (ICCCAS2006), Gui Lin, pp.2614-2617, Jun. 2006.

C25. S. Kurachi, T. Yoshimasu, K. Yamaoka, M. Nakashima, H. Liu, N. Itoh, and K. Yonemura, "Ultra-Wideband SiGe VCO with A Novel Resonant Circuit," Proc. of the 2006 International Conference on Computer & Communication Engineering (ICCCE2006), Malaysia, pp.1269-1271, May 2006.

C24. N. Itoh, "A Study of Capacitor-Coupled Varactor VCO to Investigate Flicker Noise Up-Conversion Mechanism," Proc. of the 2005 International Workshop on Radio-Frequency Integration Technology (RFIT2005), Singapore, pp.157-160, Dec. 2005.

C23. N. Itoh, "MOSFET modeling for RF circuit design," MOS-AK/ESSCIRC Workshop, Leuven, Belgium, Sep. 2004.

C22. N. Itoh, "Low Power, Low Phase Noise Integrated RF-VCO on Silicon Process," Invited talk of workshop on Asia-Pacific Microwave Conference, Kyoto, Japan, Nov. 2002.

C21. N. Itoh and S. Ishizuka "1200-MHz fully integrated VCO with "turbo-charger" technique," Proc. of the 27th 2001 European Solid-State Circuits Conference (ESSCIRC2001), Villach, Austria, pp.516-519, Sep. 2001.

C20. N. Itoh, S. Ishizuka, and K. Katoh, "Integrated LC-tuned VCO in BiCMOS process," Proc. of the 27th 2001 European Solid-State Circuits Conference (ESSCIRC2001), Villach, Austria, pp.344-347, Sep. 2001.

C19. B. De Muer, N. Itoh, M. Borremans, and M. Steyaert, "A 1.8 GHz highly-tunable low-phase-noise CMOS VCO," Digest of Technical Papers, Custom Integrated Circuits Conference, Orlando, Florida, pp.585-588, May 2000.

C18. M. Steyaert, J. Janssens, B. De Muer, M. Borremans, and N. Itoh, "A 2 Volt CMOS Cellular Transceiver Front-End," Proc. of the 2000 IEEE International Solid-State Circuits Conference (ISSCC00), San Francisco, Feb. 2000.

C17. N. Itoh, B. De Muer, and M. Steyaert, "Low supply voltage fully integrated CMOS VCO with Three terminals spiral inductor," Proc. of the 1999 IEEE European Solid-State Circuits Conference (ESSCIRC99), pp. 194-197, Duisburg, Sep. 1999.

C16. Y. Miyahara, S. Kawaguchi, S. Shimizu, N. Itoh, and K. Katoh, "A Single Chip RF-CMOS Front End LSI for GSM Handy Phone," Proc. of the 1999 International Conference on Consumer Electronics (ICCE99), pp.320-321, Jun. 1999.

C15. M. Steyaert, M. Borremans, J. Janssens, B. De Muer, N. Itoh, J. Craninckx, J. Crols, E. Morifuji, H. S. Momose, and W. Sansen, "A Single-chip CMOS Transceiver for DCS-1800 Wireless Communications," Proc. of the 1998 IEEE International Solid-State Circuits Conference (ISSCC98) , pp. 48-49, San Francisco, Feb. 1998.

C14. H. Nii, T. Yoshino, K. Inoh, N. Itoh, H. Nakajima, H. Sugaya, H. Naruse, Y. Katsumata, and H. Iwai, "0.3 μm BiCMOS technology for mixed analog/digital application systems," Proc. of the 1994 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, Sep. pp.68-71, 1997.

C13. M. Saito, M. Ono, R. Fujimoto, C. Takahashi, H. Tanimoto, N. Ito, T. Ohguro, T. Yoshitomi, H. S. Momose, and H. Iwai, "Advantage of small geometry silicon MOSFETs for high-frequency analog applications under low power supply voltage of 0.5V," Digest of Technical papers of the Symposium on VLSI Technology, pp. 71-72, Jun. 1995.

C12. N. Itoh, Y. Yoshida, S. Watanabe, Y. Katsumata, and H. Iwai, "The Analysis of Silicon Bipolar Transistor Scaling-down Scheme for Low Noise and Low Power Analog Application," Proc. of the 1994 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, Oct. pp.60-63, 1994.

C11. H. Nakajima, N. Itoh, K. Inou, T. Iinuma, S. Matsuda, C. Yoshino, Y. Katsumata, and H. Iwai, "0.5 um Silicon Bipolar Transistor Technology for Analog Applications," Proc. of the 1994 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, Oct. pp.213-216, 1994.

C10. Y. Katsumata, N. Itoh, H. Nakajima, K. Inou, T. Iinuma, S. Matsuda, C. Yoshino, Y. Tsuboi, and H. Iwai, "Sub-20 ps ECL Bipolar Technology with High Breakdown Voltage," Proc. of the 1993 IEEE European Solid-State Device Research Conference (ESSDERC 93), Grenoble, France, pp.133-136, Sep. 1993.

C9. N. Itoh, Y. Katsumata, and H. Iwai, "Noise figure degradation under emitter-base reverse stress for high-frequency bipolar ICs," Proc. of the 1993 IEEE European Solid-State Device Research Conference (ESSDERC 93), Grenoble, France, pp.727-730, Sep. 1993.

C8. S. Matsuda, N. Itoh, H. Nakajima, K. Inou, T. Iinuma, C. Yoshino, Y. Tsuboi, Y. Katsumata, H. Iwai, and H. Hara, "A Low Stress Trench Isolation Structure and Its Electrical Characteristics of Sub 20ps High-Speed ECL," Digest of Technical Papers, Symposium on VLSI Technology, Kyoto, Japan, pp.73-74, May 1993.

C7. S. Matsuda, N. Itoh, C. Yoshino, Y. Tsuboi, Y. Katsumata, and H. Iwai, "Analysis of Mechanical Stress Associated with Trench Isolation Using a Two-Dimensional Simulation," International Workshop on VLSI Process and Device Modeling: VPAD, Nara, Japan, pp.64-65, May 1993.

C6. T. Iinuma, N. Itoh, K. Inou, H. Nakajima, S. Matsuda, I. Kunishima, K. Suguro, Y. Katsumata, and H. Iwai, "A self-aligned emitter base NiSi electrode technology for advanced high-speed bipolar LSI’s," Proc. of the 1992 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, pp.104-107, Sep. 1992.

C5. K. Inou, M. Kondo, N. Itoh, Y. Tsuboi, C. Yoshino, T. Iinuma, H. Nakajima, Y. Katsumata, and H. Iwai, "Analysis of process margins for emitter-base self-aligned structures by combination of simulation and experiment," Proc. of the 1992 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, pp.113-116, Sep. 1992.

C4. N. Itoh, C. Yoshino, S. Matsuda, Y. Tsuboi, K. Inou, Y. Katsumata, and H. Iwai, "Optimization of shallow and deep trench isolation structures for ultra-high-speed bipolar LSIs," Proc. of the 1992 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Minneapolis, Sep. pp.104-107, 1992.

C3. Y. Katsumata, I. Katakabe, N. Itoh, E. Tsukioka, C. Yoshino, and H. Iwai, "Stress analysis of trench isolation structures in advanced bipolar LSIs," Proc. of the 1991 IEEE Bipolar Circuit and Technology Meeting, Minneapolis, pp.271-274, Sep. 1991.

C2. S. Nitta, T. Sugoh, H. Sugiyama, M. Nakamura, Y. Sugimoto, Y .Fukai, K. Hirakawa, H. Takada, S. Sakoh, H. Sawaya, T. Fujita, T. Miyazaki, and N. Itoh "A Variable Delay Generator for Deskew IC using ECL Gate Array," Digest of Technical Papers, Symposium on VLSI Circuits, Oiso, Japan, pp.55-56, May 1991.

C1. Y. Ushiku, T. Kobayashi, A. Yoshida, N. Itoh, A. Nishiyama, and R. Nakata, "An Optimized 1.0 um CMOS Technology for a Next Generation Channelless Gate Array," Digest of Technical Papers, Custom Integrated Circuits Conference, Portland, Oregon, U. S. A. , pp.352-355, May 1987.

著作

B1. 「RF CMOS 回路設計技術」
伊藤信之
トリケップスホワイトシリーズ, No221, ISBN4-88657-221-9, 2002年6月

B2. "Transistor Level Modeling for Analog/RF IC Design,"
Grabinski, Wladyslaw Edited
(第7章担当)
Springer, ISBN: 1-4020-4555-7, Apr. 2006.

B3.「携帯電話用RF-ICの進化と技術動向」
RFワールド No.2, CQ出版株式会社 2008年6月

翻訳書

T1. 黒田忠広 監訳
「RF マイクロエレクトロニクス」
丸善出版、ISBN:4-621-07005-3, 2002年3月

T2. 黒田忠広 監訳
「アナログCMOS集積回路の設計 応用編」
丸善出版、ISBN:4-621-07221-8, 2003年3月

T3. 黒田忠広 監訳
「アナログCMOS集積回路の設計 演習編」
丸善出版、ISBN:978-4-621-08062-7, 2009年1月

T4. 黒田忠広 監訳
「RF マイクロエレクトロニクス 第2版 実践応用編」
丸善出版、ISBN:978-4-621-08871-5, 2014年11月
最終更新日 2016.05.24